I'm Zara Patel — a Senior Electronics Engineer with 9 years of experience bridging the gap between hardware brilliance and firmware intelligence. I design circuit boards that people trust with their lives in medical devices, defence systems, and industrial automation.
From schematic capture to final production, I own the full hardware lifecycle. My work has shipped in 14 countries across 3 continents — from wearable health monitors to satellite payload controllers.
I obsess over signal integrity, power efficiency, and the kind of thermal management that lets products run for a decade without failure. If it draws current and does work, I want to optimise it.
ARM Cortex-M/A/R architecture, RTOS integration, HAL development, bootloader design, OTA firmware updates, and low-power optimisation for battery-constrained devices.
Xilinx Vivado and Intel Quartus workflows. High-speed serial interfaces, custom IP core development, DSP pipelines, timing closure, and hardware-in-loop simulation.
Antenna design & matching, LNA/PA circuits, frequency synthesisers, mixer topologies, impedance matching networks, and regulatory compliance (FCC/CE/IC).
SMPS design (buck/boost/flyback/LLC), GaN/SiC switching devices, battery management systems (BMS), MPPT solar controllers, and PFC circuits up to 10kW.
High-speed multilayer PCB layout (up to 20 layers), DDR4/5 routing, signal integrity analysis, thermal management, DFM/DFT practices, and Gerber/fabrication handoff.
End-to-end IoT hardware platform development. BLE, Zigbee, LoRaWAN, NB-IoT protocol integration, cloud connectivity, and ultra-low-power sensor node design.
Led the full hardware design of a medical-grade wearable vital signs monitor. Custom analog front-end for 12-lead ECG acquisition, photoplethysmography (PPG) for SpO₂, and accelerometer-based motion artefact cancellation. Battery life of 96 hours on 200mAh cell. FDA 510(k) cleared.
Designed FPGA-based signal processing board for Ku-band satellite ground station. Custom PCIe Gen3 interface, 10GbE data path, JESD204B ADC/DAC interface at 2.5GSPS.
Designed a 5kW on-board EV charger using GaN FETs in totem-pole PFC topology. 97.4% efficiency peak, V2G capable, CAN bus BMS integration.
Ultra-low-power sensor nodes for predictive maintenance in manufacturing. Vibration, temperature, and current sensing with 10-year coin cell lifespan.
Leading hardware development for satellite payload electronics and ground segment systems. Technical lead for a team of 6 engineers. Responsible for full-cycle PCB design, FPGA integration, and RF subsystem validation.
Hardware design engineer in the Power Management IC applications group. Developed evaluation modules (EVMs) and reference designs for TI's industrial power portfolio. Contributed to 8 product launches.
Embedded hardware engineer for automotive ECU development. AUTOSAR-compliant hardware abstraction, CAN/LIN/FlexRay interface design, and functional safety (ISO 26262 ASIL-B) compliance validation.
Available for senior hardware roles, contract PCB design, FPGA development projects, and technical consulting in RF, power electronics, and embedded systems. Open to remote and relocation.