Precision-driven electronics engineer specialising in VLSI circuit design, high-speed PCB layout, and FPGA-based digital systems — from tape-out readiness through EVT/DVT.
"Good hardware doesn't just work — it works reliably, efficiently, and elegantly for the lifetime of the product."
I'm Ryo Tanaka, a Senior Electronics Engineer based in Tokyo with a strong focus on VLSI design, FPGA-based digital systems, and mixed-signal PCB layout. My career spans consumer electronics, aerospace-grade avionics, and 5G wireless infrastructure.
I hold a B.Eng in Electronics from Tohoku University (First Class) and have spent nine years solving problems that live at the intersection of physics, mathematics, and manufacturing constraints. I work equally well with a soldering iron and an EDA tool.
Beyond design, I'm passionate about mentoring junior engineers and building design systems and review processes that scale — because great hardware is always a team achievement.
Custom CMOS cell design, place-and-route, timing closure, low-power techniques, DRC/LVS verification, and tape-out support for 16nm and 28nm process nodes.
Xilinx UltraScale+ and Intel Stratix 10 development. High-speed serial (SERDES), custom IP cores, DSP pipelines, timing closure, and hardware simulation.
Antenna design, LNA and PA circuits, frequency synthesisers, impedance matching, filter design, and full-chain link budget analysis from 400 MHz to 77 GHz.
Multilayer PCB design up to 20 layers. DDR5 routing, differential pair management, controlled impedance, HDI microvias, thermal optimisation, and Gerber handoff.
SMPS topology design (buck, boost, flyback, LLC resonant), GaN/SiC switching, battery management systems, wireless charging, and PFC up to 10kW.
ARM Cortex-M/A development, FreeRTOS and Zephyr RTOS, BLE 5.3, LoRaWAN, Matter protocol stack, ultra-low-power sensor node design, and OTA update frameworks.
Designed a 32-element phased array module for 5G NR mmWave base stations. Custom RFIC interface design, FPGA-based beamforming weight control, and 18-layer high-density PCB with integrated antenna structure. Module achieved -45 dB sidelobe suppression and passed 3GPP NR conformance testing.
Triple-redundant flight computer for UAV platform. Custom ARM + FPGA architecture, DO-178C Level A software, MIL-STD-810 environmental qualification.
Details →Custom 6T SRAM cell optimised for IoT MCU integration. Achieved 40% lower standby power vs. commercial foundry standard cell at 0.6V near-threshold operation.
Details →Totem-pole PFC bidirectional EV charger. 97.6% peak efficiency, V2G-capable, IEC 61851-1 and CHAdeMO compliant. Shipped to 3 automotive OEMs.
Details →• Owned 6-layer sensor board bring-up; cut prototype cycles with structured SI checks.
Available for senior / principal hardware roles, contract FPGA and ASIC design, PCB design consulting, and RF engineering projects. Open to Tokyo-based and international remote opportunities.